1. Field of the Invention
The invention relates to a signal-delaying loop and a method for generating a signal, particularly to a delay lock loop (DLL) and a method for generating a clock signal.
2. Description of Related Art
Generally speaking, digital electronic products need clock signals. However, when a clock signal propagates from one end of the electric circuitry to the other, the transmission lines cause extra delays, so the clock signal received by the receiving end is not synchronized to that at the transmitting end. Therefore, a delay lock loop (DLL) is often employed to synchronize the output clock signal and the input clock signal, in which a phase detector (PD) is required to compare the phases of the output clock signal and the input clock signal, such that a synchronized clock signal can be generated according to the obtained information.
FIG. 1 is a block diagram showing a conventional delay lock loop. Referring to FIG. 1, a delay lock loop 100 includes a voltage control delay line (VCDL) 110, a phase detector 120, a charge pump (CP) 130, and a low pass filter (LPF) 140. The signal CLKref is the input clock signal of the delay lock loop 100, and the signal CLKout is the output clock signal of the delay lock loop 100. The output clock signal CLKout outputted by the delay lock loop 100 is synchronized and coherent to the input clock signal CLKref of the delay lock loop 100. In the common design, the output clock signal CLKout of the delay lock loop 100 of lags by one period to the input clock signal CLKref.
FIG. 2 and FIG. 3 respectively show ideal timing diagrams of the phase detector in operation. Referring to FIGS. 1 to 3, there are two ideal conditions for the operation of the phase detector 120 herein: (1) the input clock signal CLKref and the output clock signal CLKout both have an about 50% duty cycle; and (2) the delay time of the output clock signal CLKout is between 0.5 T to 1.5 T.
In FIG. 2(a), the delay time TdL, of the output clock signal CLKout of the delay lock loop 100 is less than one period T. The clock signal at timing a is delayed by the delay time TdL after passing through the VCDL 110 and then settles at timing b. The output clock signal CLKout has to lag the input clock signal CLKref by one period T, so the phase of the clock signal at timing b has to be compared with the phase of the clock signal at timing c. In FIG. 2(a), the clock signal at timing b leads the clock signal at timing c, so the phase detector 120 sends out a down signal with a logic high (i.e. the down signal DN=1) between the rising edge of the clock signal at timing b and the rising edge of the clock signal at timing c (i.e. the interval Tph), so as to increase the delay of the voltage control delay line 110. Thus, in FIG. 2(b), the rising edge of the clock at timing b is aligned to the rising edge of the clock at timing c.
In FIG. 3(a) the delay time TdL of the output clock signal CLKout of the delay lock loop 100 is greater than one period T. The clock signal at timing a is delayed by TdL after propagating through voltage control delay line 110 and then settles at timing d. Because the output clock signal CLKout has to lag the input clock signal CLKref by one period T, the phase of the clock signal at timing d is compared with the phase of the clock signal at timing c. In FIG. 3(a), the clock signal at timing d lags the clock signal at timing c, so the phase detector 120 respectively sends out an up signal with the logic high (i.e., the up signal UP=1) between the rising edge of the clock signal at timing a and the rising edge of the clock signal at timing b (i.e. the first interval Tph) and between the rising edge of the clock signal at timing c and the rising edge of the clock signal at timing d (i.e. the second interval Tph), so as to shorten the delay time of the voltage control delay line 110. Thus, in FIG. 3(b), the rising edge of the clock signal at timing d is aligned to the rising edge of the clock signal at timing c.
FIG. 4 shows a schematic logic circuit of the phase detector in FIG. 1. The phase detector 120 is composed of two D flip flops DFF1 and DFF2, of which D ends are tied to the logic high (mentioned as “1” hereafter), wherein the input signal to the two D flip flops DFF1 and DFF2 are flipped. That is, the input clock signal CLKref is inputted to the CLK end of the D flip flop DFF1 and the CLR end of the D flip flop DFF2, and the output clock signal CLKout is inputted to the CLR end of the D flip flop DFF1 and the CLK end of the D flip flop DFF2. The D flip-flop with its D end tied to 1 operates as follows: when the end CLR=1, the D flip-flop is reset, and the end Q=0; when the end CLR=0, the CLK end changes from the logic low (mentioned as “0” hereafter) to 1, and the end Q=1.
FIG. 5 shows the timing diagram when the phase detector detects the phase difference, wherein the initial values of the up signal UP and the down signal DN are both 0. Referring to FIG. 4 and FIG. 5, at timing Ta, the input clock signal CLKref changes from 0 to 1, the output clock signal CLKout=0, and the up signal UP rises to the logic high; at timing Tb, the output clock signal CLKout changes from 0 to 1 to reset the D flip flop DFF1, and the up signal UP returns to the initial value 0. In the meanwhile, the input clock signal CLKref=1 resets the D flip flop DFF2, so the down signal DN=0.
The drawback of the conventional phase detector lies in that resetting the up signal UP and the down signal DN is determined by the input clock signal CLKref or the output clock signal CLKout with the logic high. Thus, the logic high signal being too short or too long may cause an erroneous phase detection. For example, in FIG. 6(a), at timing Ta, if the output clock signal CLKout is not 0, the up signal UP is reset; in FIG. 6(b), at timing Tb, if the input clock signal CLKref=0, the down signal DN can not be reset. The conventional phase detector would erroneously detect the signal phase in the foregoing two situations.
Therefore it is known in the art that for a conventional phase detector to operate normally, the interval Tph must be sufficiently long, and the delay of the output clock signal must be 0.5 T to 1.5 T.
Furthermore, if the clock duty of the output clock signal CLKout generated by the delay lock loop is not good, or the clock duty of the input clock signal of the delay lock loop CLKref is not good, an erroneous phase detection is caused by a conventional phase detector, and the delay lock loop can not normally operate. Because the clock duty of the clock signal varies with the processes, the power and the temperature, the delay lock loop might not be able to generate a clock signal normally due to a deteriorated clock duty.